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| 19-0866; Rev 0; 7/07 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers General Description The MAX9796 combines a high-efficiency Class D, mono audio power amplifier with a mono DirectDriveTM receiver amplifier and a stereo DirectDrive headphone amplifier. Maxim's 3rd-generation, ultra-low EMI, Class D audio power amplifiers provide Class AB performance with Class D efficiency. The MAX9796 delivers 2.3W into a 4 load from a 5V supply and offers efficiencies up to 80%. Active emissions limiting circuitry and spread-spectrum modulation greatly reduce EMI, eliminating the need for output filtering found in traditional Class D devices. The MAX9796 features a fully differential architecture, a full-bridged output, and comprehensive click-and-pop suppression. The device utilizes a flexible, user-defined mixer architecture that includes an input mixer, volume control, and output mixer. All controls are done through an I2C interface. The mono receiver amplifier and stereo headphone amplifier use Maxim's patented DirectDrive architecture, that produces a ground-referenced output from a single supply, eliminating the need for large DC-blocking capacitors, saving cost, space, and component height. The MAX9796 is available in a 36-bump UCSPTM (3mm x 3mm) package and is specified over the extended -40C to +85C temperature range. U.S. Patent # 7,061,327 Features o Unique Spread-Spectrum Modulation and Active Emissions Limiting Significantly Reduces EMI o Up to 3 Stereo Inputs o 2.3W Mono Speaker Output (4, VDD = 5V) o 50mW Mono Receiver/Stereo Headphone Outputs (32, VDD = 3.3V) o High PSRR (68dB at 217Hz) o 80% Efficiency (VDD = 3.3V, RL = 8, POUT = 600mW) o I2C Control--Input Configuration, Volume Control, Output Mode o Click-and-Pop Suppression o Low Total Harmonic Distortion (0.03% at 1kHz) o Current-Limit and Thermal Protection o Available in Space-Saving, 36-Bump UCSP (3mm x 3mm) MAX9796 Ordering Information PART MAX9796EBX+T TEMP RANGE PINPACKAGE PKG CODE B36-4 -40C to +85C 36 UCSP-36* +Denotes a lead-free package. *Four center bumps depopulated. Applications Cell Phones Portable Multimedia Players Handheld Gaming Consoles TOP VIEW (BUMPS ON BOTTOM) 1 2 3 Pin Configuration 4 5 6 Simplified Block Diagram A CPVDD C1P CPGND C1N CPVSS HPL SINGLE SUPPLY 2.7V TO 5.5V PVDD B I.C. VBIAS INC1 VSS HPR GAIN CONTROL OUT+ C PGND SDA INC2 OUTRx SCL MAX9796 INB2 VDD MIXER/ MUX I2C INTERFACE D OUTE PVDD F OUTPGND OUT+ PVDD GND SHDN INA1 INA2 INB1 I.C. MAX9796 UCSP is a trademark of Maxim Integrated Products, Inc. UCSP ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers MAX9796 ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................................+6V PVDD to PGND .......................................................................+6V CPVDD to CPGND..................................................................+6V CPVSS to CPGND .....................................................-6V to +0.3V VSS to CPGND..........................................................-6V to +0.3V C1N .......................................(CPVSS - 0.3V) to (CPGND + 0.3V) C1P.......................................(CPGND - 0.3V) to (CPVDD + 0.3V) HPL, HPR to GND...................(CPVSS - 0.3V) to (CPVDD + 0.3V) GND to PGND and CPGND................................................0.3V VDD to PVDD and CPVDD ....................................................0.3V SDA, SCL to GND.....................................................-0.3V to +6V All other pins to GND..................................-0.3V to (VDD + 0.3V) Continuous Current In/Out of PVDD, PGND, CPVDD, CPGND, OUT_ _, HPR, and HPL................................................800mA Continuous Input Current CPVSS....................................+260mA Continuous Input Current (all other pins) .........................20mA Duration of Short Circuit Between OUT+ and OUT-......................................................Continuous Duration of HP_ OUT_ Short Circuit to GND or PVDD ..........................................................Continuous Continuous Power Dissipation (TA = +70C) 36-Bump (3mm x 3mm) UCSP Multilayer Board (derate 17.0mW/C above +70C) ...........................1360.5mW Junction Temperature ......................................................+150C Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain = 0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). Speaker load resistors (RLSP) are terminated between OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted. C1 = C2 = C3 = 1F. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER GENERAL Supply Voltage Range VDD, PVDD, CPVDD Inferred from PSRR test Output mode 1, 6, 11 (Rx mode) Quiescent Current IDD Output mode 4, 9, 14 (HP mode) Output mode 2, 7, 12 (SP mode) Output mode 3, 8, 13 (SP and HP modes) Mute Current Shutdown Current IMUTE ISHDN Current in mute Hard shutdown Soft shutdown SHDN = GND See the I2C Interface section 2.7 6.3 8 11.8 15.1 4.7 0.1 8.5 30 17.5 3.5 45 1.12 28 5.5 50 1.25 1.38 41.0 8.0 5.5 10 12.6 17.5 21 10 10 15 A mA mA V SYMBOL CONDITIONS MIN TYP MAX UNITS Turn-On Time tON Time from shutdown or power-on to full operation B and C pair inputs, TA = +25C, VOL = max A pair inputs, TA = +25C, +20dB TA = +25C, VIN = 500mV IN_ inputs ms k k dB V Input Resistance Common-Mode Rejection Ratio Input DC Bias Voltage RIN CMRR VBIAS 2 _______________________________________________________________________________________ 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers ELECTRICAL CHARACTERISTICS (continued) (VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain = 0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). Speaker load resistors (RLSP) are terminated between OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted. C1 = C2 = C3 = 1F. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SPEAKER AMPLIFIER Output Offset Voltage VOS TA = +25C TMIN TA TMAX Peak voltage, TA = +25C, A-weighted, 32 samples per second (Notes 3, 4) Into shutdown Out of shutdown Into mute Out of mute VDD = 2.7V to 5.5V f = 217Hz, 100mVP-P ripple Power-Supply Rejection Ratio (Note 3) PSRR TA = +25C f = 1kHz, 100mVP-P ripple f = 20kHz, 100mVP-P ripple RL = 4, VDD = 5V, f = 1kHz Output Power (Note 4) POUT THD+N = 1%, TA = +25C RL = 8, VDD = 3.3V, f = 1kHz RL = 8, VDD = 5V, f = 1kHz Current Limit Total Harmonic Distortion Plus Noise (Note 4) RL = 8, POUT = 800mW RL = 4, POUT = 830mW SNR VOUT = 1.8VRMS, RL = 8 (Note 3) BW = 20Hz to 20kHz A-weighted 48 -62 -60 -63 -62 70 68 60 50 2300 600 1300 1.6 0.03 % 0.04 81 84 1100 1100 30 80 12 kHz A mW dB dB 5.5 23.5 40 mV SYMBOL CONDITIONS MIN TYP MAX UNITS MAX9796 Click-and-Pop Level KCP THD+N f = 1kHz Signal-to-Noise Ratio dB Fixed-frequency modulation (SSM = 0) Output Frequency fOSC Spread-spectrum modulation (SSM = 1) POUT = 470mW, f = 1kHz both channel driven, L = 68H in series with 8 load Efficiency Gain AV % dB _______________________________________________________________________________________ 3 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers MAX9796 ELECTRICAL CHARACTERISTICS (continued) (VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain = 0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). Speaker load resistors (RLSP) are terminated between OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted. C1 = C2 = C3 = 1F. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER RECEIVER AMPLIFIER Output Offset Voltage VOS TA = +25C Peak voltage, TA = +25C, A-weighted, 32 samples per second (Notes 3, 5) Into shutdown Into mute Out of shutdown Out of mute VDD = 2.7V to 5.5V f = 217Hz, 100mVP-P ripple Power-Supply Rejection Ratio (Note 3) PSRR TA = +25C f = 1kHz, 100mVP-P ripple f = 20kHz, 100mVP-P ripple Output Power Gain Total Harmonic Distortion Plus Noise Signal-to-Noise Ratio Slew Rate Capacitive Drive HEADPHONE AMPLIFIERS Output Offset Voltage VOS TA = +25C Peak voltage, TA = +25C, A-weighted, 32 samples per second (Notes 2, 5) HP_ Into shutdown Into mute Out of shutdown Out of mute Contact Air VDD = 2.7V to 5.5V f = 217Hz, 100mVP-P ripple Power-Supply Rejection Ratio (Note 3) PSRR TA = +25C f = 1kHz, 100mVP-P ripple f = 20kHz, 100mVP-P ripple 58 1.8 -61 -65 -60 -64 4 8 80 80 70 62 dB kV dB mV POUT AV THD+N SNR SR CL RL = 16 (VOUT = 800mVRMS, f = 1kHz) RL = 32 (VOUT = 800mVRMS, f = 1kHz) RL = 16, VOUT = 800mVRMS (Note 3) BW = 20Hz to 20kHz A-weighted TA = +25C, THD+N = 1% RL = 16 RL = 32 58 1.8 -62 -67 -63 -66 80 80 70 62 60 50 3 0.03 0.024 87 89 0.3 300 mW dB % dB V/s pF dB dB mV SYMBOL CONDITIONS MIN TYP MAX UNITS Click-and-Pop Level KCP Click-and-Pop Level KCP ESD Protection 4 _______________________________________________________________________________________ 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers ELECTRICAL CHARACTERISTICS (continued) (VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain = 0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). Speaker load resistors (RLSP) are terminated between OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted. C1 = C2 = C3 = 1F. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER Output Power Current Limit Gain Channel-to-Channel Gain Tracking Total Harmonic Distortion Plus Noise Signal-to-Noise Ratio Slew Rate Capacitive Drive Crosstalk VOLUME CONTROL HP gain (max) IN+6dB = 0 (minimum gain setting) Volume Control IN+6dB = 1 (maximum gain setting) SP gain (max) HP gain (min) SP gain (min) HP gain (max) SP gain (max) HP gain (min) SP gain (min) Mono Gain Input Pair A Control Mute Attenuation (Minimum Volume) DIGITAL INPUTS (SHDN, SDA, SCL) Input-Voltage High Input-Voltage Low Input Hysteresis (SDA, SCL) SDA, SCL Input Capacitance Input Leakage Current Pulse Width of Spike Suppressed VIH VIL VHYS CIN IIN tSP 50 200 10 1.0 1.4 0.4 V V mV pF A ns All outputs Mono + 6dB = 0 Mono + 6dB = 1 3 12 -72 -63 9 18 -61 -57 0 6 Set by IN+6dB 20 80 dB dB dB dB THD+N SNR SR CL L to R, R to L, f = 10kHz, RL = 16, VOUT = 160mVRMS AV TA = +25C RL = 16 (VOUT = 800mVRMS, f = 1kHz) RL = 32 (VOUT = 800mVRMS, f = 1kHz) RL = 16, VOUT = 800mVRMS BW = 20Hz to 20kHz A-weighted SYMBOL POUT TA = +25C, THD+N = 1% CONDITIONS RL = 16 RL = 32 MIN TYP 60 50 170 +3 1 0.03 0.024 92 93 0.3 300 75 MAX UNITS mW mA dB % % dB V/s pF dB MAX9796 INA+20dB = 0 (minimum gain setting) INA+20dB = 1 (maximum gain setting) VIN = 1VRMS _______________________________________________________________________________________ 5 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers MAX9796 ELECTRICAL CHARACTERISTICS (continued) (VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain = 0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). Speaker load resistors (RLSP) are terminated between OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted. C1 = C2 = C3 = 1F. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER Output Low Voltage SDA Output Fall Time SDA I2C INTERFACE TIMING Serial-Clock Frequency Bus Free Time Between STOP and START Conditions START Condition Hold STOP Condition Setup Time Clock Low Period Clock High Period Data Setup Time Data Hold Time Maximum Receive SCL/SDA Rise Time Maximum Receive SCL/SDA Fall Time Setup Time for STOP Condition Capacitive Load for Each Bus Line fSCL tBUF tHD:STA tSU:STA tLOW tHIGH tSU:DAT tHD:DAT tR tF tSU:STO Cb 0.6 400 DC 1.3 0.6 0.6 1.3 0.6 100 0 900 300 300 400 kHz s s s s s ns ns ns ns s pF SYMBOL VOL tOF ISINK = 6mA VH(MIN) to VL(MAX) bus capacitance = 10pF to 400pF, ISINK = 3mA 250 CONDITIONS MIN TYP MAX 0.4 UNITS V ns DIGITAL OUTPUTS (SDA Open Drain) Note 1: Note 2: Note 3: Note 4: All devices are 100% production tested at room temperature. All temperature limits are guaranteed by design. Measured at headphone outputs. Amplifier inputs AC-coupled to GND. Testing performed with a resistive load in series with an inductor to simulate an actual speaker load. For RL = 8 L = 68H, RL = 4 L = 47H. Note 5: Testing performed at room temperature with an 8 resistive load in series with 68H inductive load connected across BTL outputs for speaker amplifier. Testing performed with 32 resistive load connected between OUT_ and GND for headphone amplifier. Testing performed with a 32 resistive load connected between OUTRx and GND for mono receiver amplifier. Mode transitions are controlled by SHDN pin. 6 _______________________________________________________________________________________ 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers Typical Operating Characteristics (VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain = 0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). C1 = C2 = C3 = 1F. Speaker load resistors (RLSP) are terminated between OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted.) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX9796 toc01 MAX9796 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY VDD = 5V RL = 8 POUT = 500mW 0.1 THD+N (%) THD+N (%) 0.1 MAX9796 toc02 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY VDD = 3.3V RL = 4 POUT = 350mW MAX9796 toc03 1 1 1 POUT = 1W 0.1 THD+N (%) POUT = 1.6W 0.01 POUT = 750mW 0.01 0.01 POUT = 800mW VDD = 5V RL = 4 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 10 100 1k FREQUENCY (Hz) 10k 100k TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX9796 toc04 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX9796 toc05 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER VDD = 5V RL = 4 10 20Hz MAX9796 toc06 1 VDD = 3.3V RL = 8 POUT = 200mW 0.1 THD+N (%) 1 VDD = 5V RL = 8 POUT = 500mW 0.1 THD+N (%) SSM 100 THD+N (%) 1 10kHz FFM 0.01 0.01 POUT = 450mW 0.1 1kHz 0.01 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 0 0.6 1.2 1.8 2.4 3.0 OUTPUT POWER (W) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER MAX9796 toc07 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER MAX9796 toc08 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER VDD = 3.3V RL = 8 MAX9796 toc09 100 VDD = 5V RL = 8 10 100 VDD = 3.3V RL = 4 10 1kHz 10kHz 0.1 100 10 THD+N (%) THD+N (%) 1 10kHz 1 THD+N (%) 1 10kHz 0.1 0.1 20Hz 1kHz 0.01 0.01 20Hz 0.01 20Hz 1kHz 0.001 0 0.3 0.6 0.9 1.2 1.5 1.8 OUTPUT POWER (W) 0.001 0 0.2 0.4 0.6 0.8 1.0 1.2 OUTPUT POWER (W) 0.001 0 0.2 0.4 OUTPUT POWER (W) 0.6 0.8 _______________________________________________________________________________________ 7 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers MAX9796 Typical Operating Characteristics (continued) (VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain = 0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). C1 = C2 = C3 = 1F. Speaker load resistors (RLSP) are terminated between OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted.) EFFICIENCY vs. OUTPUT POWER MAX9796 toc10 EFFICIENCY vs. OUTPUT POWER MAX9796 toc11 OUTPUT POWER vs. SUPPLY VOLTAGE 3.5 OUTPUT POWER (W) 3.0 2.5 2.0 1.5 1.0 THD+N = 1% THD+N = 10% RL = 4 f = 1kHz MAX9796 toc12 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 1 2 3 OUTPUT POWER (W) VDD = 5V f = 1kHz RL = 4 RL = 8 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 0.5 1.0 OUTPUT POWER (W) 1.5 VDD = 3.3V f = 1kHz RL = 4 RL = 8 4.0 0.5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) OUTPUT POWER vs. SUPPLY VOLTAGE MAX9796 toc13 OUTPUT POWER vs. LOAD 3.5 OUTPUT POWER (W) 3.0 2.5 2.0 1.5 1.0 0.5 0 THD+N = 1% THD+N = 10% VDD = 5V f = 1kHz MAX9796 toc14 OUTPUT POWER vs. LOAD 1.4 OUTPUT POWER (W) 1.2 1.0 0.8 0.6 0.4 THD+N = 1% 0.2 0 1 10 LOAD () 100 THD+N = 10% VDD = 3.3V f = 1kHz MAX9796 toc15 2.0 1.8 1.6 OUTPUT POWER (W) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2.5 3.0 3.5 4.0 4.5 5.0 THD+N = 1% THD+N = 10% RL = 8 f = 1kHz 4.0 1.6 5.5 1 10 LOAD () 100 SUPPLY VOLTAGE (V) POWER-SUPPLY REJECTION RATIO vs. FREQUENCY MAX9796 toc16 INBAND OUTPUT SPECTRUM 0 OUTPUT MAGNITUDE (dBV) -20 -40 -60 -80 -100 -120 -140 0 5k 10k FREQUENCY (Hz) 15k 20k FIXED-FREQUENCY MODULATION MODE RL = 8 VDD = 5V f = 1kHz UNWEIGHTED VOUT = -60dBV MAX9796 toc17 INBAND OUTPUT SPECTRUM 0 OUTPUT MAGNITUDE (dBV) -20 -40 -60 -80 -100 -120 -140 0 5k 10k FREQUENCY (Hz) 15k 20k FIXED-FREQUENCY MODULATION MODE RL = 8 VDD = 5V f = 1kHz A-WEIGHTED VOUT = -60dBV MAX9796 toc18 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 10 100 1k FREQUENCY (Hz) 10k PSRR (dB) VDD = 3.3V VRIPPLE = 100mVP-P RL = 8 20 20 100k 8 _______________________________________________________________________________________ 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers Typical Operating Characteristics (continued) (VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain = 0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). C1 = C2 = C3 = 1F. Speaker load resistors (RLSP) are terminated between OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted.) INBAND OUTPUT SPECTRUM MAX9796 toc19 MAX9796 INBAND OUTPUT SPECTRUM MAX9796 toc20 WIDEBAND OUTPUT SPECTRUM FIXED-FREQUENCY MODE 0 OUTPUT MAGNITUDE (dBV) -20 -40 -60 -80 -100 -120 -140 VDD = 5V RL = 8 INPUTS AC GROUNDED 0.1 1 10 FREQUENCY (MHz) 100 1000 MAX9796 toc21 20 0 OUTPUT MAGNITUDE (dBV) -20 -40 -60 -80 -100 -120 -140 0 5k 10k FREQUENCY (Hz) 15k SPREAD-SPECTRUM MODULATION MODE RL = 8 VDD = 5V f = 1kHz UNWEIGHTED VOUT = -60dBV 20 0 OUTPUT MAGNITUDE (dBV) -20 -40 -60 -80 -100 -120 -140 0 5k 10k FREQUENCY (Hz) 15k SPREAD-SPECTRUM MODULATION MODE RL = 8 VDD = 5V f = 1kHz A-WEIGHTED VOUT = -60dBV 20 20k 20k WIDEBAND OUTPUT SPECTRUM SPREAD-SPECTRUM MODE 0 OUTPUT MAGNITUDE (dBV) -20 -40 -60 -80 -100 -120 -140 0.1 1 10 FREQUENCY (MHz) 100 1000 VDD = 5V RL = 8 INPUTS AC GROUNDED MAX9796 toc22 TURN-ON RESPONSE MAX9796 toc23 TURN-OFF RESPONSE MAX9796 toc24 20 SCL 2V/div SCL 2V/div SPEAKER OUTPUT 200mA/div SPEAKER OUTPUT 200mA/div 10ms/div 10ms/div SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9796 toc25 SHUTDOWN CURRENT vs. SUPPLY VOLTAGE MAX9796 toc26 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY VDD = 5V RL = 32 MAX9796 toc27 16 INPUTS AC GROUNDED 14 0.25 INPUTS AC GROUNDED SHUTDOWN CURRENT (A) 0.20 1 SUPPLY CURRENT (mA) 0.1 0.15 THD+N (%) POUT = 20mW 0.01 0.05 POUT = 40mW 0.001 2.5 3.0 3.5 4.0 4.5 5.0 5.5 10 100 1k FREQUENCY (Hz) 10k 100k SUPPLY VOLTAGE (V) 12 0.10 10 8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 8 _______________________________________________________________________________________ 9 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers MAX9796 Typical Operating Characteristics (continued) (VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain = 0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). C1 = C2 = C3 = 1F. Speaker load resistors (RLSP) are terminated between OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted.) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX9796 toc28 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX9796 toc29 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER VDD = 5V RL = 32 10 f = 1kHz THD+N (%) MAX9796 toc30 1 VDD = 3.3V RL = 16 1 VDD = 3.3V RL = 32 100 0.1 THD+N (%) THD+N (%) POUT = 40mW 0.1 POUT = 40mW 1 f = 10kHz 0.1 0.01 POUT = 20mW 0.01 POUT = 10mW 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 10 100 1k FREQUENCY (Hz) 10k 100k 0.01 f = 20Hz 0.001 0.001 0 20 40 60 80 OUTPUT POWER (mW) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER MAX9796 toc31 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER VDD = 3.3V RL = 32 10 f = 1kHz MAX9796 toc32 TOTAL HARMONIC DISTORTION PLUS NOISE vs. COMMON-MODE VOLTAGE VDD = 3.3V fIN = 1kHz POUT = 30mW GAIN = +3dB RL = 32 MAX9796 toc33 100 VDD = 3.3V RL = 16 10 f = 1kHz f = 10kHz 100 100 10 THD+N (%) f = 10kHz 0.1 0.1 THD+N (%) 1 THD+N (%) 1 1 0.1 0.01 f = 20Hz 0.001 0 30 60 90 OUTPUT POWER (mW) 120 0.01 f = 20Hz 0.001 0 20 40 60 80 OUTPUT POWER (mW) 0.01 0.001 0 0.5 1.0 1.5 2.0 COMMON-MODE VOLTAGE (V) 2.5 POWER DISSIPATION vs. OUTPUT POWER MAX9796 toc34 POWER DISSIPATION vs. OUTPUT POWER 450 POWER DISSIPATION (mW) 400 350 300 250 200 150 100 50 0 120 0 40 80 RL = 32 VDD = 3.3V f = 1kHz POUT = POUTR + POUTL 120 160 RL = 16 MAX9796 toc35 OUTPUT POWER vs. SUPPLY VOLTAGE MAX9796 toc36 500 450 POWER DISSIPATION (mW) 400 350 300 250 200 150 100 50 0 0 40 80 TOTAL OUTPUT POWER (mW) VDD = 5V f = 1kHz RL = 32 POUT = POUTR + POUTL 500 65 60 THD+N = 10% OUTPUT POWER (mW) 55 50 45 40 35 30 2.7 3.2 3.7 4.2 4.7 5.2 RL = 32 f = 1kHz THD+N = 1% TOTAL OUTPUT POWER (mW) SUPPLY VOLTAGE (V) 10 ______________________________________________________________________________________ 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers Typical Operating Characteristics (continued) (VDD = PVDD = CPVDD = 3.3V, GND = PGND = CPGND = 0V, SHDN = VDD, I2C settings (INA gain = +20dB, INB gain = INC gain = 0dB, volume setting = 0dB, mono path gain = 0dB, SHDN = 1, SSM = 1). C1 = C2 = C3 = 1F. Speaker load resistors (RLSP) are terminated between OUT+ and OUT-, headphone load resistors are terminated to GND, unless otherwise noted.) OUTPUT POWER vs. LOAD MAX9796 toc37 MAX9796 OUTPUT POWER vs. LOAD MAX9796 toc38 OUTPUT POWER vs. LOAD RESISTANCE AND CHARGE-PUMP CAPACITOR SIZE VDD = 3.3V f = 1kHz THD+N = 1% C1 = C2 = 2.2F 60 C1 = C2 = 1F MAX9796 toc39 200 180 160 OUTPUT POWER (mW) 140 120 100 80 60 40 20 0 10 100 LOAD () THD+N = 1% VDD = 5V f = 1kHz THD+N = 10% 200 180 160 OUTPUT POWER (mW) 140 120 100 80 60 40 20 0 THD+N = 1% THD+N = 10% VDD = 3.3V f = 1kHz 100 80 OUTPUT POWER (mW) 40 20 C1 = C2 = 0.68F 0 10 100 LOAD () 1000 10 100 LOAD RESISTANCE () 1000 1000 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY MAX9796 toc40 OUTPUT FREQUENCY SPECTRUM 0 OUTPUT MAGNITUDE (dBV) -20 -40 -60 -80 -100 -120 -140 0 5k 10k FREQUENCY (Hz) 15k 20k VDD = 3.3V f = 1kHz RL = 32 MAX9796 toc41 0 POWER-SUPPLY REJECTION RATIO (dB) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 10 100 1k 10k FREQUENCY (Hz) HPL HPR VDD = 3.3V VIN = 100mVP-P RL = 32 20 100k CROSSTALK vs. FREQUENCY 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 10 MAX9796 toc42 CROSSTALK vs. INPUT AMPLITUDE fIN = 1kHz RL = 32 GAIN = +3dB MAX9796 toc43 OUT_ = 1VP-P RL = 32 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 CROSSTALK (dB) RIGHT TO LEFT CROSSTALK (dB) RIGHT TO LEFT LEFT TO RIGHT 100 1k 10k FREQUENCY (Hz) 100k LEFT TO RIGHT 0.4 0.8 INPUT AMPLITUDE (VRMS) 1.2 ______________________________________________________________________________________ 11 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers MAX9796 Pin Description BUMP A1 A2 A3 A4 A5 A6 B1, F1, F5 B2, E6 B3 B4 B5 B6 C1, F4 C2 C5 C6 D1, F3 D2 D5 D6 E1, F2 E2 E3 E4 E5 F6 NAME CPVDD C1P CPGND C1N CPVSS HPL PVDD I.C. VBIAS INC1 VSS HPR OUT+ SDA INC2 OUTRx PGND SCL INB2 VDD OUTSHDN INA1 INA2 INB1 GND Charge-Pump Power Supply Charge-Pump Flying Capacitor Positive Terminal Charge-Pump GND Charge-Pump Flying Capacitor Negative Terminal Charge-Pump Output. Connect to VSS. Left Headphone Output Class D Power Supply Internal Connection. Leave unconnected. This pin is internally connected to the signal path. Do not connect together or to any other pin. Common-Mode Bias Input C1. Left input or positive input (see Table 5a). Headphone Amplifier Negative Power Supply. Connect to CPVSS. Right Headphone Output Positive Speaker Output Serial Data Input. Connect a 1k pullup resistor from SDA to VDD. Input C2. Right input or negative input (see Table 5a). Mono Receiver Output Power Ground Serial Clock Input. Connect a 1k pullup resistor from SCL to VDD. Input B2. Right input or negative input (see Table 5a). Analog Power Supply Negative Speaker Output Active-Low Hardware Shutdown Input A1. Left input or positive input (see Table 5a). Input A2. Right input or negative input (see Table 5a). Input B1. Left input or positive input (see Table 5a). Analog Ground FUNCTION 12 ______________________________________________________________________________________ 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers Typical Application Circuit VDD VDD MAX9796 C2 1F CPVSS A5 C1N A4 C1 1F VDD CPGND A3 C1P A2 CPVDD A1 C3 1F 1F INA1 E3 INA2 E4 1F 1F INB1 E5 INB2 D5 1F 1F INC1 B4 INC2 C5 1F VBIAS 1F C2 B3 INPUT C: 0dB OR 6dB INPUT B: 0dB OR 6dB INPUT MIXER MONO VOLUME INPUT A: 0dB, 6dB, OR 20dB LEFT VOLUME RIGHT VOLUME CHARGE PUMP VSS B5 VDD D6 1F PVDD F1, B1, F5 0.1F 1F DirectDrive 3dB A6 HPL 3dB B6 HPR OUTPUT MIXER 3dB C6 OUTRx 12dB C1, F4 OUT+ CLASS D AMPLIFIER E1, F2 OUT- SDA SCL SHDN MAX9796 D2 E2 I2C CONTROL F6 GND PGND D1 F3 PGND ______________________________________________________________________________________ 13 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers MAX9796 Detailed Description The MAX9796 ultra-low-EMI, filterless, Class D audio power amplifier features several improvements to switch-mode amplifier technology. The MAX9796 features active emissions limiting circuitry to reduce EMI. Zero dead-time technology maintains state-of-the-art efficiency and THD+N performance by allowing the output FETs to switch simultaneously without crossconduction. A unique filterless modulation scheme and a spread-spectrum modulation create a compact, flexible, low-noise, efficient audio power amplifier while occupying minimal board space. The differential input architecture reduces common-mode noise pickup with or without the use of input-coupling capacitors. The MAX9796 can also be configured as a single-ended input amplifier without performance degradation. The MAX9796 features three fully differential input pairs (INA_, INB_, INC_) that can be configured as stereo single-ended or mono differential inputs. I2C provides control for input configuration, volume level, and mixer configuration. DirectDrive allows the headphone and mono receiver amplifiers to output ground-referenced signals from a single supply, eliminating the need for large DC-blocking capacitors. Comprehensive clickand-pop suppression minimizes audible transients during the turn-on and turn-off of amplifiers. Class D Speaker Amplifier Comparators monitor the audio inputs and compare the complementary input voltages to a sawtooth waveform. The comparators trip when the input magnitude of the sawtooth exceeds their corresponding input voltage. The active emissions limiting circuitry slightly reduces the turn-on rate of the output H-bridge by slew-rate limiting the comparator output pulse. Both comparators reset at a fixed time after the rising edge of the second comparator trip point, generating a minimum-width pulse (tON(MIN), 100ns typ) at the output of the second comparator (Figure 1). As the input voltage increases or decreases, the duration of the pulse at one output increases while the other output pulse duration remains the same. This causes the net voltage across the speaker (VOUT+ - VOUT-) to change. The minimumwidth pulse helps the device to achieve high levels of linearity. tSW VIN- VIN+ OUT- OUT+ tON(MIN) VOUT+ - VOUT- Figure 1. Outputs with an Input Signal Applied 14 ______________________________________________________________________________________ 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers Operating Modes Fixed-Frequency Modulation The MAX9796 features a fixed-frequency modulation mode with a 1.1MHz switching frequency, set through the I2C interface (Table 2). In fixed-frequency modulation mode, the frequency spectrum of the Class D output consists of the fundamental switching frequency and its associated harmonics (see the Wideband Output Spectrum Fixed-Frequency Mode graph in the Typical Operating Characteristics). Spread-Spectrum Modulation The MAX9796 features a unique, patented spreadspectrum modulation that flattens the wideband spectral components. Proprietary techniques ensure that the cycle-to-cycle variation of the switching period does not degrade audio reproduction or efficiency (see the Typical Operating Characteristics). Select the spreadspectrum modulation mode through the I2C interface (Table 2). In spread-spectrum modulation mode, the switching frequency varies randomly by 30kHz around the center frequency (1.16MHz). The modulation scheme remains the same, but the period of the sawtooth waveform changes from cycle to cycle (Figure 2). Instead of a large amount of spectral energy present at multiples of the switching frequency, the energy is now spread over a bandwidth that increases with frequency. Above a few megahertz, the wideband spectrum looks like white noise for EMI purposes (see Figure 3). MAX9796 tSW tSW tSW tSW VIN- VIN+ OUT- OUT+ tON(MIN) VOUT+ - VOUT- Figure 2. Output with an Input Signal Applied (Spread-Spectrum Modulation Mode) ______________________________________________________________________________________ 15 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers MAX9796 40 35 EN55022B LIMIT 30 AMPLITUDE (dBV/m) 25 20 15 10 5 30 60 80 100 120 140 160 180 200 220 240 260 280 300 FREQUENCY (MHz) Figure 3. EMI with 76mm of Speaker Cable VIN = 0V consumption, especially when idling. When no signal is present at the input of the MAX9796, the outputs switch as shown in Figure 4. Because the MAX9796 drives the speaker differentially, the two outputs cancel each other, resulting in no net idle mode voltage across the speaker, minimizing power consumption. DirectDrive OUT- OUT+ VOUT+ - VOUT- = 0V Figure 4. Outputs with No Input Signal Filterless Modulation/Common-Mode Idle The MAX9796 uses Maxim's unique, patented modulation scheme that eliminates the LC filter required by traditional Class D amplifiers, improving efficiency, reducing component count, conserving board space and system cost. Conventional Class D amplifiers output a 50% dutycycle square wave when no signal is present. With no filter, the square wave appears across the load as a DC voltage, resulting in finite load current, increasing power 16 Traditional single-supply headphone amplifiers have outputs biased at a nominal DC voltage (typically half the supply) for maximum dynamic range. Large coupling capacitors are needed to block this DC bias from the headphone. Without these capacitors, a significant amount of DC current flows to the headphone, resulting in unnecessary power dissipation and possible damage to both headphone and headphone amplifier. Maxim's patented DirectDrive architecture uses a charge pump to create an internal negative supply voltage. This allows the headphone outputs of the MAX9796 to be biased at GND, almost doubling dynamic range while operating from a single supply. With no DC component, there is no need for the large DC-blocking capacitors. Instead of two large (220F, typ) tantalum capacitors, the MAX9796 charge pump requires two small ceramic capacitors, conserving board space, reducing cost, and improving the frequency response of the headphone amplifier. See the Output Power vs. Load Resistance and Charge-Pump Capacitor Size graph in the Typical Operating Characteristics for details of the possible capacitor sizes. There is a low DC voltage on the driver outputs ______________________________________________________________________________________ 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers due to amplifier offset. However, the offset of the MAX9796 is typically 1.4mV, which, when combined with a 32 load, results in less than 44nA of DC current flow to the headphones. In addition to the cost and size disadvantages of the DC-blocking capacitors required by conventional headphone amplifiers, these capacitors limit the amplifier's low-frequency response and can distort the audio signal. Previous attempts at eliminating the output-coupling capacitors involved biasing the headphone return (sleeve) to the DC bias voltage of the headphone amplifiers. This method raises some issues: 1) The sleeve is typically grounded to the chassis. Using the midrail biasing approach, the sleeve must be isolated from system ground, complicating product design. 2) During an ESD strike, the driver's ESD structures are the only path to system ground. Thus, the amplifier must be able to withstand the full ESD strike. 3) When using the headphone jack as a lineout to other equipment, the bias voltage on the sleeve may conflict with the ground potential from other equipment, resulting in possible damage to the amplifiers. VOUT MAX9796 VDD VOUT VDD / 2 GND CONVENTIONAL DRIVER-BIASING SCHEME +VDD GND Charge Pump The MAX9796 features a low-noise charge pump. The switching frequency of the charge pump is half the switching frequency of the Class D amplifier, regardless of the operating mode. The nominal switching frequency is well beyond the audio range, and thus does not interfere with the audio signals, resulting in an SNR of 93dB. Although not typically required, additional high-frequency noise attenuation can be achieved by increasing the size of C2 (see the Typical Application Circuit). The charge pump is active in both speaker and headphone modes. -VDD DirectDrive BIASING SCHEME Figure 5. Traditional Amplifier Output vs. MAX9796 DirectDrive Output Signal Path The audio inputs of the MAX9796 (INA, INB, and INC) are preamplified and then mixed by the input mixer to create three internal signals: left (L), right (R), and mono (M). Tables 5a and 5b show how the inputs are mixed to create L, R, and M. These signals are then independently volume adjusted by the L, R, and M volume control and routed to the output mixer. The output mixer mixes the internal L, R, and M signals to create a variety of audio mixes that are output to the headphone, speaker, and the mono receiver amplifiers. Figure 6 shows the signal path that the audio signals take. Signal amplification takes place in three stages. In the first stage, the inputs (INA, INB, and INC) are preamplified. The amount by which each input is amplified is determined by the bits INA+20dB (B4 in the Input Mode Control Register) and IN+6dB (B3 in the Global Control Register). After preamplification, they are mixed in the input mixer to create the internal signals L, R and M. In the second stage of amplification, the internal L, R, and M signals are independently volume adjusted. Finally, each output amplifier has its own internal gain. The speaker, headphone, and mono receiver amplifiers have fixed gains of 12dB, 3dB and 3dB, respectively. ______________________________________________________________________________________ 17 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers MAX9796 -75dB TO 0dB 12dB SPEAKER RVOL PREAMPLIFIER INPUT INPUT A: 0dB, 6dB, 20dB INPUT B AND C: 0dB, 6dB MONO MONO+6dB MVOL INPUT MIXER LVOL 0dB OR 6dB -75dB TO 0dB 3dB RECEIVER -75dB TO 0dB OUTPUT MIXER 3dB HEADPHONE Figure 6. Signal Path Current-Limit and Thermal Protection The MAX9796 features current limiting and thermal protection to protect the device from short circuits and overcurrent conditions. The headphone amplifier pulses in the event of an overcurrent condition with a pulse every 100s as long as the condition is present. Should the current still be high, the above cycle is repeated. The speaker amplifier current-limit protection clamps the output current without shutting down the output. This can result in a distorted output. Current is limited to 1.6A in the speaker amplifiers and 170mA in the headphone and mono receiver amplifiers. The MAX9796 has thermal protection that disables the device at +150C until the temperate decreases to +120C. headphone amplifier does not require output-coupling capacitors, this problem does not arise. In most applications, the output of the preamplifier driving the MAX9796 has a DC bias of typically half the supply. During startup, the input-coupling capacitor is charged to the preamplifier's DC bias voltage, resulting in a DC shift across the capacitor and an audible clickand-pop. An internal delay of 30ms eliminates the clickand-pop caused by the input filter. Shutdown The MAX9796 features a 0.1A hard shutdown mode that reduces power consumption to extend battery life and a soft shutdown where current consumption is typically 8.5A. Hard shutdown is controlled by connecting SHDN to GND, disabling the amplifiers, bias circuitry, charge pump, and I2C. In shutdown, the headphone amplifier output impedance is 1.4k and the speaker output impedance is 300k. Similarly, the MAX9796 enters soft shutdown when the SHDN bit = 0 (see Table 2). The I2C interface is active and the contents of the command register are not affected when in soft shutdown. This allows the master to write to the MAX9796 while in shutdown. The I2C interface is completely disabled in hardware shutdown. When the MAX9796 is reenabled the default settings are applied (see Table 3). Click-and-Pop Suppression In conventional single-supply headphone amplifiers, the output-coupling capacitor is a major contributor of audible clicks and pops. Upon startup, the amplifier charges the coupling capacitor to its bias voltage, typically half the supply. Likewise, during shutdown, the capacitor is discharged to GND. This results in a DC shift across the capacitor, which in turn, appears as an audible transient at the speaker. Since the MAX9796 18 ______________________________________________________________________________________ 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers MAX9796 SDA tSU, DAT tLOW SCL tHD, STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD, DAT tSU, STA tBUF tHD, STA tSP tSU, STO Figure 7. 2-Wire Serial-Interface Timing Diagram I2C Interface The MAX9796 features an I2C 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX9796 and the master at clock rates up to 400kHz. Figure 7 shows the 2-wire interface timing diagram. The MAX9796 is a receive-only slave device relying on the master to generate the SCL signal. The master, typically a microcontroller, generates SCL and initiates data transfer on the bus. The MAX9796 cannot write to the SDA bus except to acknowledge the receipt of data from the master. The MAX9796 does not acknowledge a read command from the master. A master device communicates to the MAX9796 by transmitting the proper address followed by the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse. The MAX9796 SDA line operates as both an input and an open-drain output. A pullup resistor, greater than 500, is required on the SDA bus. The MAX9796 SCL line operates as an input only. A pullup resistor, greater than 500, is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9796 from highvoltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. SCL S Sr P SDA Figure 8. START, STOP, and REPEATED START Conditions Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). SDA and SCL idle high when the I2C bus is not busy. START and STOP Conditions A master device initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 8). A START condition from the master signals the beginning of a transmission to the MAX9796. The master terminates transmission and frees the bus by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. ______________________________________________________________________________________ 19 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers MAX9796 Early STOP Conditions The MAX9796 recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. Slave Address The MAX9796 is available with one preset slave address (see Table 1). The address is defined as the seven most significant bits (MSBs) followed by the read/write (R/W) bit. The address is the first byte of information sent to the MAX9796 after the START condition. The MAX9796 is a slave device only capable of being written to. The R/W bit should be a zero when configuring the MAX9796. Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX9796 uses to handshake receipt of each byte of data (see Figure 9). The MAX9796 pulls down SDA during the master-generated 9th clock pulse. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may reattempt communications. Write Data Format A write to the MAX9796 includes transmission of a START condition, the slave address with the R/W bit set to 0 (Table 1), one byte of data to configure the Command Register, and a STOP condition. Figure 10 illustrates the proper format for one frame. The MAX9796 only accepts write data, but it acknowledges the receipt of the address byte with the R/W bit set high. The MAX9796 does not write to the SDA bus in the event that the R/W bit is set high. Subsequently, the master reads all 1's from the MAX9796. Always set the R/W bit to zero to avoid this situation. Programming the MAX9796 The MAX9796 is programmed through six control registers. Each register is addressed by the three MSBs (B5-B7) followed by five configure bits (B0-B4) as shown in Table 2. Correct programming of the MAX9796 requires writing to all six control registers. Upon poweron, their default settings are as listed in Table 3. Table 1. MAX9796 Address Map SLAVE ADDRESS A6 1 A5 0 A4 0 CLOCK PULSE FOR ACKNOWLEDGMENT A3 1 A2 1 A1 0 A0 1 R/W 0 START CONDITION SCL 1 2 COMMAND BYTE IS STORED ON RECEIPT OF STOP CONDITION ACKNOWLEDGE FROM MAX9796 S SLAVE ADDRESS R/W B7 B6 B5 B4 B3 B2 B1 B0 8 NOT ACKNOWLEDGE 9 0 ACK COMMAND BYTE ACKNOWLEDGE FROM MAX9796 ACK P SDA ACKNOWLEDGE Figure 9. Acknowledge Figure 10. Write Data Format Example Table 2. Control Registers FUNCTION Input Mode Control Mono Volume Control Left Volume Control Right Volume Control Output Mode Control Global Control Register B7 0 0 0 0 1 1 B6 COMMAND 0 0 1 1 0 0 0 1 0 1 0 1 MONO+6dB SHDN IN+6dB INA+20dB B5 B4 B3 DATA INMODE (Tables 5a and 5b) MVOL (Table 7) LVOL (Table 7) RVOL (Table 7) OUTMODE (Table 9) MUTE SSM MONO B2 B1 B0 20 ______________________________________________________________________________________ 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers MAX9796 Table 3. Power-On Reset Conditions COMMAND Input Mode (000) Mono Volume (001) Left Volume (010) Right Volume (011) Output Mode (100) Global Control Register (101) DATA 10000 11111 11111 11111 01000 00011 Maximum volume Maximum volume Maximum volume Mode 8: stereo headphone, mono speaker Powered-off, input B/C gain = 0dB, MUTE off, SSM on, MONO on DESCRIPTION Input A gain = +20dB; input A, B, and C singled-ended stereo inputs Input Mode Control The MAX9796 has three flexible inputs that can be configured as single-ended stereo inputs or differential mono inputs. All input signals are summed into three unique signals, Left (L), Right (R), and Mono (M), which are routed to the output amplifiers. The bit B4 allows the option of boosting low-level signals on INA. B4 can be set as follows: 1 = Input A's gain +20dB for low-level signals such as FM receivers. 0 = Input A's gain is either 0dB or +6dB as set by IN+6dB (bit B3 of the Control Register). Tables 5a and 5b show how the inputs-INA, INB, and INC-are mixed to create the internal signals left (L), right (R), and mono (M). Table 4. Input Mode Control Register B7 Input Mode Control 0 B6 0 B5 0 B4 INA+20dB B3 B2 B1 B0 INMODE (Tables 5a and 5b ) Table 5a. Input Mode PROGRAMMING MODE INMODE B3 0 0 0 0 0 0 0 0 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 B1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 INA1 L L L L L L M+ M+ M+ M+ M+ M+ INA2 R R R R R R MMMMMMINPUT CONFIGURATION INB1 L L M+ M+ R+ L+ L L M+ M+ R+ L+ INB2 R R MMRLR R MMRLINC1 L M+ L M+ L+ R+ L M+ L M+ L+ R+ INC2 R MR MLRR MR MLR- ______________________________________________________________________________________ 21 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers MAX9796 Table 5b. Internal Signals L, R, and M PROGRAMMING MODE B3 0 0 0 0 0 0 0 0 1 1 1 1 INMODE B2 B1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 INTERNAL SIGNALS LEFT (L), RIGHT (R), AND MONO (M) L INA1 + INB1 + INC1 INA1 + INB1 INA1 + INC1 INA1 INA1 + (INC1 - INC2) INA1 + (INB1 - INB2) INB1 + INC2 INB1 INC1 -- INC1 - INC2 INB1 - INB2 R INA2 + INB2 + INC2 INA2 + INB2 INA2 + INC2 INA2 INA2 + (INB1 - INB2) INA2 + (INC1 - INC2) INB2 + INC2 INB2 INC2 -- INB1 - INB2 INC1 - INC2 M -- INC1 - INC2 INB1 - INB2 (INB1 - INB2) + (INC1 INC2) -- -- INA1 - INA2 (INA1 - INA2) + (INC1 INC2) (INA1 - INA2) + (INB1 INB2) (INA1 - INA2) + (INB1 INB2) INA1 - INA2 INA1 - INA2 Mono/Left/Right Volume Control The MAX9796 has separate volume control for each of the internal signals: left (L), right (R), and mono (M). The final gain of each signal is determined by the way the following bits are set: MVOL, LVOL, RVOL, INA+20dB, IN+6dB, and MONO+6dB. Table 7 shows how to configure the L, R, and M amplifiers for specific gains. Table 6. Mono/Left/Right Volume Control Registers B7 Mono Volume Control Left Volume Control Right Volume Control 0 0 0 B6 0 1 1 B5 1 0 1 B4 B3 B2 MVOL LVOL RVOL B1 B0 Table 7. Volume Control Settings MVOL/LVOL/RVOL B4 0 0 0 0 0 0 0 0 B3 0 0 0 0 0 0 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 GAIN (dB) Mute -75 -71 -67 -63 -59 -55 -51 MVOL/LVOL/RVOL B4 0 0 0 0 0 0 0 0 B3 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 GAIN (dB) -47 -44 -41 -38 -35 -32 -29 -26 22 ______________________________________________________________________________________ 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers MAX9796 Table 7. Volume Control Settings (continued) MVOL/LVOL/RVOL B4 1 1 1 1 1 1 1 1 B3 0 0 0 0 0 0 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 GAIN (dB) -23 -21 -19 -17 -15 -13 -11 -9 MVOL/LVOL/RVOL B4 1 1 1 1 1 1 1 1 B3 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 GAIN (dB) -7 -6 -5 -4 -3 -2 -1 0 Output Mode Control MONO+6dB in the Output Mode Control register allows an extra 6dB of gain on the internal mono signal: 1 = Additional 6dB of gain is applied to the internal Mono (M) signal path. 0 = No additional gain is applied to the Internal Mono (M) signal path. The MAX9796 has four output amplifiers: a mono receiver amplifier, a stereo DirectDrive headphone amplifier, and one mono Class D amplifier. Table 8. Output Mode Control Register B7 Output Mode Control 1 B6 0 B5 0 B4 Mono+6dB B3 B2 B1 B0 OUTMODE (Table 9) Table 9 shows how each of the three internal signals, left (L), right (R), and mono (M), are mixed and routed to the various outputs. Table 9. Output Modes MODE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OUTMODE B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RECEIVER -- M -- -- -- -- L+R -- -- -- -- M+L+R -- -- -- MUTE LEFT HP -- -- -- M M -- -- -- L L -- -- -- L+M L+M MUTE RIGHT HP -- -- -- M M -- -- -- R R -- -- -- R+M R+M MUTE SPK -- -- M M -- -- -- L+R L+R -- -- -- L+R+M L+R+M -- MUTE -- = Amplifier off, R = Right signal L = Left signal, M = Mono signal ______________________________________________________________________________________ 23 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers MAX9796 Global Control Register The Global Control Register is used for global configurations, those affecting all inputs and outputs. The bits in the Control Register affect the inputs and outputs as shown in Table 11. Table 10. Global Control Register B7 Global Control Register 1 B6 0 B5 1 B4 SHDN B3 IN+6dB B2 MUTE B1 SSM B0 MONO Table 11. Global Control Register Configurations BIT B4 NAME SHDN FUNCTION 1 = Normal operation. 0 = Low-power shutdown mode. I2C settings are saved. 1 = All input signals are boosted by 6dB. 0 = All input signals are passed unamplified. This bit does not affect INA if the INA+20dB bit (B4 of the Input Mode Control Register) is set to 1, in which case INA is boosted by 20dB. 1 = Mute all outputs. 0 = All outputs are active. 1 = Spread-spectrum Class D modulation. 0 = Fixed-frequency Class D modulation. 1 = Speaker outputs L+R in modes 7, 8, 12, and 13 (see Table 9). 0 = Speaker outputs L in modes 7, 8, 12, and 13 (see Table 9). B3 IN+6dB B2 B1 B0 MUTE SSM MONO Applications Information Class D Filterless Operation Traditional Class D amplifiers require an output filter to recover the audio signal from the amplifier's PWM output. The filters add cost, increase the solution size of the amplifier, and can decrease efficiency. The traditional PWM scheme uses large differential output swings (2 x VDD(P-P)) and causes large ripple currents. Any parasitic resistance in the filter components results in a loss of power, lowering the efficiency. The MAX9796 does not require an output filter. The device relies on the inherent inductance of the speaker coil and the natural filtering of both the speaker and the human ear to recover the audio component of the square-wave output. Eliminating the output filter results in a smaller, less costly, more efficient solution. Because the switching frequency of the MAX9796 speaker output is well beyond the bandwidth of most speakers, voice coil movement due to the square-wave frequency is very small. Although this movement is small, a speaker not designed to handle the additional power may be damaged. For optimum results, use a speaker with a series inductance >10H. Typical 8 speakers, for portable audio applications, exhibit series inductances in the range of 20H to 100H. Input Amplifier Differential Input The MAX9796 features a programmable differential input structure, making it compatible with many CODECs, and offering improved noise immunity over a single-ended input amplifier. In devices such as cellular phones, high-frequency signals from the RF transmitter can be picked up by the amplifier's input traces. The signals appear at the amplifier's inputs as common-mode noise. A differential input amplifier amplifies the difference of the two inputs and any signal common to both is cancelled. 24 ______________________________________________________________________________________ 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers Single-Ended Input The MAX9796 can be configured as a single-ended input amplifier by appropriately configuring the Input Control Register (see Tables 5a and 5b). DC-Coupled Input The input amplifier can accept DC-coupled inputs that are biased to the amplifier's bias voltage. DC-coupling eliminates the input-coupling capacitors; reducing component count to potentially six external components (see the Typical Application Circuit). However, the highpass filtering effect of the capacitors is lost, allowing low-frequency signals to feed through to the load. Unused Inputs Connect any unused input directly to VBIAS. This saves input capacitors on unused inputs and provides the highest noise immunity on the input. on the frequency range of the spoken human voice (typically 300Hz to 3.5kHz). In addition, speakers used in portable devices typically have a poor response below 300Hz. Taking these two factors into consideration, the input filter may not need to be designed for a 20Hz to 20kHz response, saving both board space and cost due to the use of smaller capacitors. MAX9796 Component Selection Input Filter An input capacitor (CIN) in conjunction with the input impedance of the MAX9796 forms a highpass filter that removes the DC bias from the incoming signal. The ACcoupling capacitor allows the amplifier to automatically bias the signal to an optimum DC level. Assuming zero source impedance, the -3dB point of the highpass filter is given by: f-3dB = 1 2RINCIN Class D Output Filter The MAX9796 does not require a Class D output filter. The device passes EN55022B emissions standards with 152mm of unshielded speaker cables. However, output filtering can be used if a design is failing radiated emissions due to board layout or cable length, or the circuit is near EMI-sensitive devices. Use a ferrite bead filter when radiated frequencies above 10MHz are of concern. Use an LC filter when radiated frequencies below 10MHz are of concern, or when long leads (>152mm) connect the amplifier to the speaker. Figure 11 shows optional speaker amplifier output filters. External Component Selection BIAS Capacitor VBIAS is the output of the internally generated DC bias voltage. The VBIAS bypass capacitor, CVBIAS improves PSRR and THD+N by reducing power supply and other noise sources at the common-mode bias node, and also generates the clickless/popless, startup/shutdown DC bias waveforms for the speaker amplifiers. Bypass VBIAS with a 1F capacitor to GND. 22 Choose CIN so that f-3dB is well below the lowest frequency of interest. Use capacitors whose dielectrics have low-voltage coefficients, such as tantalum or aluminum electrolytic. Capacitors with high-voltage coefficients, such as ceramics, may result in increased distortion at low frequencies. Other considerations when designing the input filter include the constraints of the overall system and the actual frequency band of interest. Although high-fidelity audio calls for a flat-gain response between 20Hz and 20kHz, portable voice-reproduction devices, such as cell phones and two-way radios, need only concentrate 0.1F 33H OUT_+ 0.47F OUT_33H 0.1F 22 0.033F 0.033F Figure 11. Speaker Amplifier Output Filter ______________________________________________________________________________________ 25 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers MAX9796 Charge-Pump Capacitor Selection Use capacitors with an ESR less than 100m for optimum performance. Low-ESR ceramic capacitors minimize the output resistance of the charge pump. Most surface-mount ceramic capacitors satisfy the ESR requirement. For best performance over the extended temperature range, select capacitors with an X7R dielectric or better. Table 12 lists suggested manufacturers. Flying Capacitor (C1) The value of the flying capacitor (C1) affects the output resistance of the charge pump. A C1 value that is too small degrades the device's ability to provide sufficient current drive, which leads to a loss of output voltage. Increasing the value of C1 reduces the charge-pump output resistance to an extent. Above 1F, the on-resistance of the switches and the ESR of C1 and C2 dominate. Output Capacitor (C2) The output capacitor value and ESR directly affect the ripple at CPVSS. Increasing the value of C2 reduces output ripple. Likewise, decreasing the ESR of C2 reduces both ripple and output resistance. Lower capacitance values can be used in systems with low maximum output power levels. See the Output Power vs. Load Resistance and Charge-Pump Capacitor Size graph in the Typical Operating Characteristics. CPVDD Bypass Capacitor (C3) The CPVDD bypass capacitor (C3) lowers the output impedance of the power supply and reduces the impact of the MAX9796's charge-pump switching transients. Bypass CPVDD with C3 to PGND and place it physically close to the CPVDD and PGND. Use a value for C3 that is equal to C1. parasitic trace resistance. Large traces also aid in moving heat away from the package. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any switching noise from coupling into the audio signal. Connect PGND and GND together at a single point on the PCB. Route all traces that carry switching transients away from GND and the traces/components in the audio signal path. Connect all of the power-supply inputs (CPVDD, VDD, and PVDD) together. Bypass CPVDD with a 1F capacitor to CPGND. Bypass VDD with a 1F capacitor to GND. Bypass PVDD with a 1F capacitor in parallel with a 0.1F capacitor to PGND. Place the bypass capacitors as close as possible to the MAX9796. Place a bulk capacitor between PVDD and PGND, if needed. Use large, low-resistance output traces. Current drawn from the outputs increase as load impedance decreases. High output trace resistance decreases the power delivered to the load. Large output, supply, and GND traces allow more heat to move from the MAX9796 to the PCB, decreasing the thermal impedance of the circuit. UCSP Applications Information For the latest application details on UCSP construction, dimensions, tape carrier information, PCB techniques, bump-pad layout, and recommended reflow temperature profile, as well as the latest information of reliability testing results, refer to Application Note: UCSP--A Wafer-Level Chip-Scale Package available on Maxim's website at www.maxim-ic.com/ucsp. UCSP Thermal Consideration When operating at maximum output power, the UCSP thermal dissipation can become a limiting factor. The UCSP package does not dissipate heat as efficiently as packages with a thermal pad. As a result, in some applications, the thermal performance of the package may limit performance. Supply Bypassing, Layout, and Grounding Proper layout and grounding are essential for optimum performance. Use large traces for the power-supply inputs and amplifier outputs to minimize losses due to Table 12. Suggested Capacitor Manufacturers SUPPLIER Taiyo Yuden TDK PHONE 800-348-2496 847-803-6100 FAX 847-925-0899 847-390-4405 WEBSITE www.t-yuden.com www.component.tdk.com Chip Information PROCESS: BiCMOS 26 ______________________________________________________________________________________ 2.3W, High-Power Class D Audio Subsystem with DirectDrive Headphone Amplifiers Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 36L,UCSP.EPS MAX9796 PACKAGE OUTLINE, 6x6 UCSP 21-0082 K 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. |
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